A useful application in integrated circuits is a frequency multiplier, in which an input signal of one frequency is multiplied by a fixed integer to create a signal of a higher frequency. For example, the output of a clock circuit at one frequency may be multiplied by an integer to generate a higher frequency clock signal.
Various ways to do frequency multiplication are known in the art. For example, a delay locked loop having N elements may be used, and taps taken from each of the N elements which are then combined to create a number of clock edges that is N times higher than the frequency that is applied to the delay locked loop.
Typically, the limiting factor in such a frequency multiplier, or other similar multipliers, is that the multiplier circuit may, due to inaccuracies in its implementation, generate jitter in the edge positions. Jitter means that the positions of each of the newly generated edges ate not precisely where they should be, i.e., the new edges in between the edges of the original signal are not located at precisely the equidistant positions that a mathematical calculation would predict.
For example, a device intended to multiply an input dock signal of 5 megahertz (MHz) by four will create four output pulses, and thus 8 output edges rather than the 2 output edges of the original 5 MHz input signal. These newly generated edges may each systematically deviate from the ideal equidistant times at which they are desired to occur. In one circuit, the first edge, which should occur after 25 nanoseconds (NS), might occur at 24 NS, the second edge, which should occur at 50 NS, might occur at 53 NS, etc.
Many designers, if not most, will assume that the deviation from the ideal position of each of the newly generated dock edges is random, i.e., noise created by a Gaussian distribution of undesired frequencies around the desired frequency. The most common way that most designers will try to correct for this is by using a high-Q filter to narrow the range of noise, although high-Q filters are difficult to implement well and are not easily adjustable if the desired clock frequency changes.
What most designers fail to realize, however, is that such jitter comes from two effects. One effect is a random variation of the edge position, such as is widely believed. But the other effect is a systematic variation in edge position due to repeatable artifacts in the elements of the circuit mechanism being used to multiply the signal.
The systematic type of variation gives rise to a characteristic non-random error that repeats in each cycle of the applied input signal, i.e., the error in the position of the clock edges will to a large degree be the same during the next cycle of the input frequency because the same error is present on each of the output phases for each input signal. This type of jitter is sometimes known as “fixed pattern jitter,” because it thus repeats in a pattern over some time interval, i.e., at fixed frequencies, typically the time interval of the input clock signal.
FIG. 1 shows a curve 100 of the Fourier transform of (i.e., the frequencies contained in) a 20 MHz signal created by multiplying a 5 MHz signal by 4 as above. As expected, the peak response is in the middle of the x-axis, at 20 MHz, and noise appearing on either side of this peak response primarily at frequency intervals of 5 MHz, with the two closest frequencies, 15 MHz and 25 MHz, being the highest intensity of the noise frequencies. If the edge positions are plotted as a deviation from their ideal positions, the signal represented by the Fourier transform of FIG. 1 is shown in FIG. 2, in which curve 202 shows the positive edge error and curve 204 shows the negative edge error. The edges vary from their ideal positions by as much as +4 NS.
As will be apparent to one of skill in the art, any signal with a repeating pattern may be described as a spectrum consisting of discrete values, i.e., a Fourier transform. Thus, if these discrete tones in the spectrum can be suppressed, the fixed pattern portion of the jitter may be greatly reduced or eliminated.
It is thus desirable to construct a circuit that is able to eliminate such fixed pattern jitter in clock multiplier and other types of circuits.